A turbo encoder is a standard component in, e.g., 3G wireless communication systems for Wideband Code Division Multiple Access (W-CDMA). A turbo encoder implements turbo convolutional coding (TCC), one type of which is recursive systematic convolutional coding, an advanced forward error correction algorithm. The encoder receives an input data stream (e.g., a digitized voice signal) and feeds into a communication channel (e.g., a wireless transmission link) an output data stream generated based on the input. The output data stream is a multiplexed stream including the input data stream and two (or more) encoded parity data streams. The parity streams carry the recursive encoded information about the input stream and provide redundancy for correcting errors, e.g., due to noise in the communication channel. In addition, one of the parity streams is generated using interleaving (i.e., reordering in a systematic way) to disperse burst errors, which makes them easier to correct at a receiver. The parity streams may optionally be punctured to save bandwidth.
FIG. 1 illustrates a representative turbo encoder 100 of the prior art. Encoder 100 includes two recursive systematic convolutional (RSC) encoders 102a–b, an interleaver 104, and a multiplexer (MUX) 106. Input data stream 110 (typically comprising a sequence of data packets (blocks) of variable size) is replicated to form three copies, with MUX 106, RSC encoder 102a, and interleaver 104 each receiving one copy. Interleaver 104 operates by receiving a payload of a data packet (data block) and pseudo-randomizing (interleaving) it, e.g., as specified in 3G Partnership Project Technical Specification Document (3GPP TS) 25.212 v.4.2.0. The interleaved data block is then fed into RSC encoder 102b. The outputs of encoders 102a–b and a copy of stream 110 are combined in MUX 106 to generate output data stream 120 of encoder 100.
One problem with encoder 100 is a substantial processing delay between the time a data block has been shifted in and the time the encoder can begin to output the corresponding multiplexed data stream. For example, for a data block that is K bits long, the processing delay may be about 2K clock cycles. In addition, encoder 100 is typically configured to generate and store a separate copy of the interleaved data block and/or corresponding addresses in addition to the originally received data block. This requires additional memory and may increase the chip area and cost for encoder 100.